Today's integrated circuits include a vast number of devices. Smaller devices are key to enhance performance and to improve reliability. As MOSFET (Metal Oxide Semiconductor Field-Effect-Transistor, a name with historic connotations meaning in general an insulated gate Field-Effect-Transistor) devices are being scaled down, the technology becomes more complex and new methods are needed to maintain the expected performance enhancement from one generation of devices to the next.
One of the most important indicators of potential device performance is the carrier mobility. There is great difficulty in keeping carrier mobility high in devices of deeply submicron generations. A promising avenue toward better carrier mobility is to modify the semiconductor that serves as raw material for device fabrication. It has been known, and recently further studied, that tensilely or compressively straining semiconductors have intriguing carrier properties. In particular, a 90–95% improvement in the electron mobility has been achieved in a strained silicon (Si) channel NMOS as described in U.S. Pat. No. 6,649,492 B2 to J. O. Chu entitled “Strained Si Based Layer Made By UHV-CVD, and Devices Therein” incorporated herein by reference. Similarly for hole enhancement, compressively-strained buried germanium (Ge) MODFETs have yielded high hole mobilities as described by S. J. Koester, et. al. in “Extremely high transconductance Ge/Si0.4Ge0.6 p-MODFET's grown by UHV-CVD, “IEEE Elect. Dev. Lett. 21, 110 (2000), and in U.S. patent application “High Speed Ge-Channel SiGe/Ge/SiGe Heterostructure for Field Effect Transistor” by J. O. Chu, Ser. No. 09/936,320 filed Sep. 12, 2000, incorporated herein by reference. Combination of tensilely and compressively strained SiGe regions in the same wafer is described in U.S. patent application “Dual Strain-State SiGe Layers for Microelectronics” by J. O. Chu, Ser. No. 10/389,145, filed Mar. 15, 2003, incorporated herein by reference.
Because of its enhanced hole mobility there is renewed technological interest in Ge-based MOSFET devices for high performance CMOS logic. In particular, surface channel Ge MOSFET devices, using oxynitride (GeON) as the gate insulator, have been demonstrated by H. Shang et al, IEDM, p. 441, 2002. Or, using high-K as the gate insulator, Ge PMOS is described in the following references: C. Chui et al, IEDM, p. 437, 2002, C. H. Huang et al, VLSI symp. p. 119, 2003 and A. Ritenour et al, IEDM, p. 433, 2003 all three of which are incorporated herein by reference.
Buried channel strained Ge PMOS have also been reported having hole mobility enhancement as described in the following references of M. Lee et al, IEDM, p. 429 2003 and H. Shang et.al, VLSI symp. 2004 both of which are incorporated herein by reference. Nonetheless, the Ge devices reported have employed simple device structures, such as ring type gate structure lay-out for simplified integration, and usually have relative large dimensions. Such features are not or suitable for integration into advanced high performance CMOS technologies.
A process compatible with standard CMOS technology, in order to incorporate strained Ge structures for enhanced hole mobility in PMOS devices, is not available.